Microcontrollers may be based on one or more so-called cores, a system bus, other system bus masters, a memory subsystem and peripheral modules, where the memory subsystem includes a flash memory with a pre-fetch buffer mechanism. Internal bus architectures of these devices typically range from 32-bits to 64-bits wide. The flash memory and pre-fetch buffers are typically significantly wider than the system bus. In fact, most often the flash line width is aligned with the width of the system cache lines which is typically 256-bits in currently existing high-end systems.
The flash memory typically has a relatively slow access time in relation to the speed of the core accessing the memory. For example a typical system with a core frequency of 200 MHz or more may have in the region of seven or more cycles to make a read directly from the flash. A pre-fetch buffer mechanism is therefore usually used which aims to improve the overall throughput of data flow from the flash to an accessing master by making speculative data fetches from the flash and storing this data in a small memory array. In this way the data may be fetched and ready to be accessed before the master has requested the access. A problem may arise when the pre-fetch mechanism makes a speculative pre-fetch of data that is not immediately required by the accessing master. This data fetch is usually non-abortable due to the architecture of the flash memory. Then, any further flash accesses must wait for this access to complete which may reduce overall system performance. Further, this unnecessary pre-fetch consumes valid buffer space and removes data fetched at an earlier occasion from the buffer, which may increase the likelihood of another flash access being necessary. This may have a detrimental impact on overall system performance, in contrast to the aim of the pre-fetch buffer mechanism. These effects may especially arise when the executable code comprises one or more Change of Flows (COFs), i.e., instructions that cannot fetched from a linearly incrementing address, but from a distant target address. It may thus be desirable to minimize the number of unnecessary speculative pre-fetches made to the flash memory, especially in a multi-core system which shares a single flash memory or other type of non-volatile memory (NVM).